[PATCH] D87464: [TargetLowering] Improve SimplifyDemandedBits for AND and OR

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1208
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
     if (SimplifyDemandedBits(Op0, ~Known.Zero & DemandedBits, DemandedElts,
                              Known2, TLO, Depth + 1))
----------------
Pull out
```
APInt Op0DemandedBits = ~Known.Zero & DemandedBits;
```


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1225
       SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
           Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
       SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
----------------
Op0DemandedBits ?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1227
       SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
           Op1, DemandedBits, DemandedElts, TLO.DAG, Depth + 1);
       if (DemandedOp0 || DemandedOp1) {
----------------
Op1DemandedBits ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D87464/new/

https://reviews.llvm.org/D87464