[PATCH] D93750: [RISCV] Frame handling for RISC-V V extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:496
     Register Reg = Entry.getReg();
+    // We don't have sensible DWARF for VRs yet
+    if (RISCV::VRRegClass.contains(Reg))
----------------
jrtc27 wrote:
> :( is there progress being made to specify it?
After rethinking it, there is no callee-saved vector registers in the current specification. I think we could remove the if statement.

Reference: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc


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https://reviews.llvm.org/D93750