[PATCH] D93750: [RISCV] Frame handling for RISC-V V extension.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/MachineFrameInfo.h:226
+  /// vector objects have been allocated yet.
+  bool HasScalableVectorObjects = false;
+
----------------
jrtc27 wrote:
> How come SVE doesn't need this already?
I didn't dig into how SVE implements it. I will do some study.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:547
     const RISCVRegisterInfo *RI = STI.getRegisterInfo();
-    if (RI->needsStackRealignment(MF)) {
+    if (RI->needsStackRealignment(MF) && !MFI.hasScalableVectorObjects()) {
       Align MaxAlignment = MFI.getMaxAlign();
----------------
StephenFan wrote:
> why if the machine function has the scalable vector objects, then the prolog doesn't need to realign the stack address ?
I need to think about how to deal with it when there are objects needed realignment and RVV objects on the stack at the same time.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:249
   bit HasDummyMask = 0;
+  bit IsRVVLoadStore = 0;
 }
----------------
jrtc27 wrote:
> Can you not just do `isa<>` to check it's the right class and then look at mayLoad/mayStore?
Good idea! Thanks for your tips.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93750/new/

https://reviews.llvm.org/D93750