[PATCH] D93705: [RISCV] Define vector mask-register logical intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:577
+  def int_riscv_vmxnor: RISCVBinaryAAXNoMask;
+  def int_riscv_vmmv: RISCVUnaryNoMask;
+  def int_riscv_vmnot: RISCVUnaryNoMask;
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I don't think we need vmmv and vmnot. Those can be macros in the frontend.


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  https://reviews.llvm.org/D93705/new/

https://reviews.llvm.org/D93705