[PATCH] D93705: [RISCV] Define vector mask-register logical intrinsics.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:198
+  // Input: (vl)
+  class RISCVNullaryNoMask
+        : Intrinsic<[llvm_anyvector_ty],
----------------
This isn't used.


================
Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:569
 
+  def int_riscv_vmand: RISCVBinaryAAXNoMask;
+  def int_riscv_vmnand: RISCVBinaryAAXNoMask;
----------------
This should be AAA not AAX. The second argument is the same as the result.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:180
+  ValueType Mask = Mas;
+  int SEW = Sew;
+  LMULInfo LMul = M;
----------------
Can you add the comments to these that appear in our downstream repo?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:192
+  def : MTypeInfo<vbool2_t, 8, V_M4>;
+  def : MTypeInfo<vbool1_t, 8, V_M1>;
+}
----------------
This line has M8 in our downstream repo.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll:3
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.nxv1i1(
+  <vscale x 1 x i1>,
----------------
We shouldn't need to say nxv1i1 twice. This will be fixed by using AAA instead of AAX in the  Intrinsics file


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll:73
+  ret <vscale x 8 x i1> %a
+}
----------------
Why does the test only go up to v8i1? Aren't there isel patterns for v16i1/v32i1/v64i1 as well?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93705/new/

https://reviews.llvm.org/D93705