[PATCH] D93608: [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll:14
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
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Is the earlyclobber constraint not working here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93608/new/

https://reviews.llvm.org/D93608