[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

> I was wondering if we could do something like (with a0=lo and a1=hi):
>
>   vmv.v.x vX, a1
>   vsll.vx vX, vX, /*32*/
>   vor.vx vX, vX, a0
>
> And then do a `.vv` operation.
>
> We can then optimize for a sign-extended 32-bit value later. What do you think?

Sounds good idea, but seems like it's correctness issue rather than optimization issue, we can't guarantee the bit 31 isn't 1 unless it's constant literal, the upper-half will become all-1 if it's 1, so...we need 3 more instructions + 1 temp vector reg.

  vmv.v.x vX, a1
  vsll.vx vX, vX, /*32*/
  vmv.v.x vY, a0
  vsll.vx vY, vY, /*32*/
  vsrl.vx vY, vY, /*32*/
  vor.vv vX, vX, vY

and I guess we could borrow FPR for rv32ifdv*:

- load value to fa0
- vfmv.v.f vX, fa0


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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312