[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D93312#2460414 <https://reviews.llvm.org/D93312#2460414>, @kito-cheng wrote:

> Supported but it might not working as you expected...IIRC it will sign-extend the content of 32 bit reg to 64 bit and then doing a vector-scalar operation.
>
> But maybe you could code gen that by following code seq:
>
> - push scalar value into stack.
> - load via a stride loads with 0 stride as splat load.
> - vector-vector operation.

Oh yes I see that now, thanks Section 11.1:

> Vector-scalar operations can have three possible forms, but in all cases take one vector of operands from a vector register group specified by vs2 and a second scalar source operand from one of three alternative sources.
> For integer operations, the scalar can be a 5-bit immediate encoded in the rs1 field. The value is sign-extended to SEW bits, unless otherwise specified. . For integer operations, the scalar can be taken from the scalar x register specified by rs1. If XLEN>SEW, the least-significant SEW bits of the x register are used, unless otherwise specified. If XLEN<SEW, the value from the x register is sign-extended to SEW bits.

I was wondering if we could do something like (with a0=lo and a1=hi):

  vmv.v.x vX, a1
  vsll.vx vX, vX, /*32*/
  vor.vx vX, vX, a0

And then do a `.vv` operation.

We can then optimize for a sign-extended 32-bit value later. What do you think?


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