[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D93312#2460779 <https://reviews.llvm.org/D93312#2460779>, @kito-cheng wrote:

> Sounds good idea, but seems like it's correctness issue rather than optimization issue, we can't guarantee the bit 31 isn't 1 unless it's constant literal, the upper-half will become all-1 if it's 1, so...we need 3 more instructions + 1 temp vector reg.
>
>   vmv.v.x vX, a1
>   vsll.vx vX, vX, /*32*/
>   vmv.v.x vY, a0
>   vsll.vx vY, vY, /*32*/
>   vsrl.vx vY, vY, /*32*/
>   vor.vv vX, vX, vY
>
> and I guess we could borrow FPR for rv32ifdv*:
>
> - load value to fa0
> - vfmv.v.f vX, fa0

Oh good point, thanks. Interestingly enough riscv-ovpsim didn't clobber the upper bits when I tried running it, but reading the spec I think we agree it should have.


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