[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

> Also, it will not handle 64-bit scalars in RV32, but I don't believe that's
> actually supported in the spec?

Supported but it seems not working as you expected...IIRC it will sign-extend the content of 32 bit reg to 64 bit and then doing a vector-scalar operation.

But maybe you could code gen that by following code seq:

- push scalar value into stack.
- load via a stride loads with 0 stride as splat load.
- vector-vector operation.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312