[PATCH] D93365: [RISCV] Add intrinsics for vmv.x.s and vmv.s.x

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This adds intrinsics for vmv.x.s and vmv.s.x.

I've used stricter type constraints on these intrinsics than what we've been doing on the arithmetic intrinsics so far. This will allow us to not need to pass the scalar type to the Intrinsic::getDeclaration call when creating these intrinsics. Because of this I had to add custom ISD opcodes for isel since type legalization of the scalar to XLenVT breaks the constraint. DAG ISel will inherit constraints from the intrinsics if we use them in an isel pattern. A custom ISD opcode for vmv.x.s was needed anyway in order to implement the change in computeNumSignBitsForTargetNode.

I also modified the MC layer description of these instructions to show the tied source/dest operand. This is different than what we do for masked instructions where we drop the tied source operand when converting to MC. But it is a more accurate description of the instruction. We can't do this for masked instructions since we use the same MC instruction for masked and unmasked. Tools like llvm-mca operate in the MC layer and rely on ins/outs and Uses/Defs for analysis so I don't know if we'll be able to maintain the current behavior for masked instructions. So I went with the accurate description here since it was easy.


https://reviews.llvm.org/D93365

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll

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