[PATCH] D93364: [RISCV] Load/Store vector mask types.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D93364#2463535 <https://reviews.llvm.org/D93364#2463535>, @craig.topper wrote:

> In D93364#2463053 <https://reviews.llvm.org/D93364#2463053>, @HsiangKai wrote:
>
>> In D93364#2462311 <https://reviews.llvm.org/D93364#2462311>, @craig.topper wrote:
>>
>>> In D93364#2462242 <https://reviews.llvm.org/D93364#2462242>, @HsiangKai wrote:
>>>
>>>> D93368 <https://reviews.llvm.org/D93368> will depend on this commit. For example, there are four vector arguments in the masked version of vmseq, i.e., maskedoff, varg0, varg1, mask. When LMUL = 4, we could pass the arguments varg0 and varg1 through vector registers. The first mask type argument will be put in v0. The second mask type argument, i.e., mask, will pass through stack. The address will be stored in the GPR. We need to load the mask value from the stack. Vector argument passing is another issue. We could create another patch for it.
>>>
>>> Are you saying the tests in D93368 <https://reviews.llvm.org/D93368> don't pass without this commit?
>>
>> Yes, I mean the test cases for LMUL = 4 and LMUL = 8 will not pass without this commit.
>
> My concern is that I'm not convinced that something like this is correct
>
>   %a = alloca <vscale x 32 x i1>
>   %b = store <vscale x 32 x i1> %c, <vscale x 32 x i1>* %a
>
> getTypeSize for that alloca woud return a scalable result with a fixed size of 32. Would we still end up allocating (vlen / 8) * 64 bytes on the stack for that. Or would it be (vlen / 8) * 32 bytes?

We could use the size of one vector register as the unit to allocate stack for RVV objects. Even the size of mask type variable is smaller than one vector register. We could allocate one vector register size for it. It is similar for fractional LMUL variables. There are whole register load/store in v1.0 to access RVV objects in the stack for LMUL = 1, 2, 4, 8.

In our downstream implementation, there is a snippet to calculate how many vectors to reserve in the stack for RVV objects.

  int64_t ObjectSize = MFI.getObjectSize(FI);
  
  unsigned ShiftAmount;
  // Mask objects may be logically smaller than the spill size of the VR
  // class.
  if (ObjectSize <= TRI->getSpillSize(RISCV::VRRegClass))
    ShiftAmount = 0;
  else if (ObjectSize == TRI->getSpillSize(RISCV::VRM2RegClass))
    ShiftAmount = 1;
  else if (ObjectSize == TRI->getSpillSize(RISCV::VRM4RegClass))
    ShiftAmount = 2;
  else if (ObjectSize == TRI->getSpillSize(RISCV::VRM8RegClass))
    ShiftAmount = 3;
  else
    llvm_unreachable("Unexpected object size");


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