[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:347
+
+    for (auto VT : MVT::integer_scalable_vector_valuetypes())
+      setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
----------------
I'm not sure this should be all scalable types. Typically we only mark the legal types.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:417
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass, ImmType>;
+  }
----------------
This might not catch all immediates it could. The operand of the splat_vector is going to be XLenVT. When the scalar element type is less than XLenVT, only some of the bits of the splat_vector operand are going to be used so the other bits should be ignored for the purposes of checking if the immediate is simm5. We might get lucky because DAGTypeLegalizer::PromoteIntRes_Constant prefers sign_extend.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93312/new/

https://reviews.llvm.org/D93312