[PATCH] D93312: [RISCV] Add ISel support for RVV .vx and .vi forms

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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This patch extends the SDNode ISel support for RVV vadd to the
vector/scalar and vector/immediate forms. It uses splat_vector to carry
the scalar in each case.

I will flesh out the tests if the general idea is approved.

Also, it will not handle 64-bit scalars in RV32, but I don't believe that's
actually supported in the spec?

Authored-by: Roger Ferrer Ibanez <rofirrim at gmail.com>
Co-Authored-by: Fraser Cormack <fraser at codeplay.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D93312

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

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