[PATCH] D92973: [RISCV] Add intrinsics for vsetvli instruction
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 9 18:59:22 PST 2020
craig.topper updated this revision to Diff 310744.
craig.topper added a comment.
Fix typo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D92973/new/
https://reviews.llvm.org/D92973
Files:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D92973.310744.patch
Type: text/x-patch
Size: 7935 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201210/ad87c461/attachment.bin>
More information about the llvm-commits
mailing list