[PATCH] D92973: [RISCV] Add intrinsics for vsetvli instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 310711.
craig.topper added a comment.

Disabling isel if V extension isn't enabled.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92973/new/

https://reviews.llvm.org/D92973

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

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