[PATCH] D92228: [RISCV] Add MIR tests exposing missed InstAliases

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a subscriber: arcbbb.
craig.topper added a comment.

Adding @arcbbb. Him and I were talking about maybe splitting masked and unmasked into separate instructions. We need to prevent masked instructions from using v0 as a destination. To do that we've been using @earlyclobber, but that prevents any source operand from being the same as the destination. To fix this it might be better to have separate masked and unmasked instructions. Then we won't use @earlyclobber and instead make the masked instruction forbid v0 as a destination with a register class constraint. Not sure how many additional instructions and pseudo instructions that will require. Thoughts?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D92228/new/

https://reviews.llvm.org/D92228