[PATCH] D92228: [RISCV] Add MIR tests exposing missed InstAliases

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Nov 29 23:00:26 PST 2020

HsiangKai added a comment.

In D92228#2421866 <https://reviews.llvm.org/D92228#2421866>, @craig.topper wrote:

> Adding @arcbbb. Him and I were talking about maybe splitting masked and unmasked into separate instructions. We need to prevent masked instructions from using v0 as a destination. To do that we've been using @earlyclobber, but that prevents any source operand from being the same as the destination. To fix this it might be better to have separate masked and unmasked instructions. Then we won't use @earlyclobber and instead make the masked instruction forbid v0 as a destination with a register class constraint. Not sure how many additional instructions and pseudo instructions that will require. Thoughts?

Initially, I implemented the V instructions using separate classes for masked and unmasked instructions. You could see the difference from

We need to define some additional classes for masked instructions. After that, we could use multiclass to define unmasked/masked instructions at once.

  rG LLVM Github Monorepo



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