[PATCH] D92105: [RISCV] Add pre-emit pass to make more instructions compressible
Craig Blackmore via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 25 08:03:41 PST 2020
craigblackmore created this revision.
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When optimizing for size, this pass searches for instructions that are
prevented from being compressed by one of the following:
1. The use of a single uncompressed register.
2. A base register + offset where the offset is too large to be compressed and the base register may or may not already be compressed.
In the first case, if there is a compressed register available, then the
uncompressed register is copied to the compressed register and its uses
replaced. This is only done if there are enough uses that code size
would be improved.
In the second case, if a compressed register is available, then the
original base register is copied and adjusted such that:
new_base_register = base_register + adjustment
base_register + large_offset = new_base_register + small_offset
and the uses of the base register are replaced with the new base
register. Again this is only done if there are enough uses for code size
to be improved.
This patch includes the logic for optimizing SW/LW instructions but the
logic for other instructions could also be added in the same manner.
This pass was authored by Lewis Revill, with large offset optimization
added by Craig Blackmore.
rG LLVM Github Monorepo
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