[PATCH] D92104: [RegisterScavenging] Fix assert in scavengeRegisterBackwards

Craig Blackmore via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 25 08:03:01 PST 2020

craigblackmore created this revision.
craigblackmore added reviewers: MatzeB, arsenm.
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According to the documentation, if a spill is required to make a
register available and AllowSpill is false, then NoRegister should be
returned, however, this scenario was actually triggering an assertion


This patch moves the assertion after the handling of AllowSpill.


Authored by: Lewis Revill

  rG LLVM Github Monorepo



Index: llvm/lib/CodeGen/RegisterScavenging.cpp
--- llvm/lib/CodeGen/RegisterScavenging.cpp
+++ llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -573,7 +573,6 @@
   MCPhysReg Reg = P.first;
   MachineBasicBlock::iterator SpillBefore = P.second;
-  assert(Reg != 0 && "No register left to scavenge!");
   // Found an available register?
   if (SpillBefore == MBB.end()) {
     LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
@@ -584,6 +583,8 @@
   if (!AllowSpill)
     return 0;
+  assert(Reg != 0 && "No register left to scavenge!");
   MachineBasicBlock::iterator ReloadAfter =
     RestoreAfter ? std::next(MBBI) : MBBI;
   MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);

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