[PATCH] D91842: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma node in tablegen. Remove explicit commuted patterns from targets.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 20 03:29:35 PST 2020
RKSimon added inline comments.
================
Comment at: llvm/include/llvm/Target/TargetSelectionDAG.td:444
+def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>;
def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
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Can fmad be updated as well?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91842/new/
https://reviews.llvm.org/D91842
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