[PATCH] D91842: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma node in tablegen. Remove explicit commuted patterns from targets.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 19 22:14:16 PST 2020


craig.topper created this revision.
craig.topper added reviewers: efriedma, RKSimon, spatel.
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X86 was already specially marking fma as commutable which allowed
tablegen to autogenerate commuted patterns. This moves it to the target
independent definition and fix up the targets to remove now
unneeded patterns.

Unfortunately, the tests change because the commuted version of
the patterns are generating operands in a different than the
explicit patterns.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91842

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/lib/Target/Hexagon/HexagonPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrFMA.td
  llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
  llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
  llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

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