[PATCH] D91842: [SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma node in tablegen. Remove explicit commuted patterns from targets.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 306828.
craig.topper added a comment.

Make fmad commutable as well. Looks like only AMDGPU uses it and I don't think they have patterns that care.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91842/new/

https://reviews.llvm.org/D91842

Files:
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/lib/Target/Hexagon/HexagonPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrFMA.td
  llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
  llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
  llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir
  llvm/test/CodeGen/ARM/fp16-fusedMAC.ll
  llvm/test/CodeGen/RISCV/double-arith.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-fma-loops.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/ternary.ll

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