[PATCH] D91730: [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6b0fc1f3c161: [RISCV] Add MemOperand to the instruction created by… (authored by craig.topper).
Herald added a subscriber: jrtc27.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91730/new/

https://reviews.llvm.org/D91730

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/select-optimize-multiple.ll


Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -222,14 +222,13 @@
 ; RV32I-NEXT:    sw a4, 12(sp)
 ; RV32I-NEXT:    fld ft0, 8(sp)
 ; RV32I-NEXT:    sw a1, 8(sp)
-; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    fld ft1, 8(sp)
 ; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    bnez a0, .LBB5_2
-; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    fmv.d ft1, ft0
+; RV32I-NEXT:    sw a2, 12(sp)
+; RV32I-NEXT:    beqz a0, .LBB5_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    fld ft0, 8(sp)
 ; RV32I-NEXT:  .LBB5_2: # %entry
-; RV32I-NEXT:    fsd ft1, 8(sp)
+; RV32I-NEXT:    fsd ft0, 8(sp)
 ; RV32I-NEXT:    lw a0, 8(sp)
 ; RV32I-NEXT:    lw a1, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -119,8 +119,13 @@
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  unsigned Opcode;
+  MachineFunction *MF = MBB.getParent();
+  const MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineMemOperand *MMO = MF->getMachineMemOperand(
+      MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
+      MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
+  unsigned Opcode;
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::SW : RISCV::SD;
@@ -134,7 +139,8 @@
   BuildMI(MBB, I, DL, get(Opcode))
       .addReg(SrcReg, getKillRegState(IsKill))
       .addFrameIndex(FI)
-      .addImm(0);
+      .addImm(0)
+      .addMemOperand(MMO);
 }
 
 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -146,8 +152,13 @@
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  unsigned Opcode;
+  MachineFunction *MF = MBB.getParent();
+  const MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineMemOperand *MMO = MF->getMachineMemOperand(
+      MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
+      MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
+  unsigned Opcode;
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::LW : RISCV::LD;
@@ -158,7 +169,10 @@
   else
     llvm_unreachable("Can't load this register from stack slot");
 
-  BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
+  BuildMI(MBB, I, DL, get(Opcode), DstReg)
+    .addFrameIndex(FI)
+    .addImm(0)
+    .addMemOperand(MMO);
 }
 
 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,


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