[PATCH] D91730: [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Is the code change due to the fact that the optimizer later finally knows that `12(sp)` and `8(sp)` don't overlap?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91730/new/

https://reviews.llvm.org/D91730