[PATCH] D91730: [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 18 14:07:01 PST 2020

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HsiangKai accepted this revision.
HsiangKai added a comment.
This revision is now accepted and ready to land.

LGTM.


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https://reviews.llvm.org/D91730

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