[PATCH] D91712: [RISCV] Use register class VR for V instruction operands directly.

[Hsiangkai Wang via Phabricator via llvm-commits]

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@tangxingxin1008 found a bug that regard `vadd.vv v1, v3, a0` as a valid V instruction. We should remove the `VRegAsmOperand` operand class and use `VR` register class directly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91712

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/invalid.s

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