[PATCH] D91668: [RISCV]Add register constraint on riscv vector instruction

Wed Nov 18 05:19:01 PST 2020

HsiangKai added a comment.

In D91668#2401481 <https://reviews.llvm.org/D91668#2401481>, @tangxingxin1008 wrote:

> In D91668#2401307 <https://reviews.llvm.org/D91668#2401307>, @craig.topper wrote:
>
>> In D91668#2401279 <https://reviews.llvm.org/D91668#2401279>, @jrtc27 wrote:
>>
>>> I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both `(reg)` and `0(reg)`, but that's irrelevant for vectors.
>>
>> I was wondering the same thing.
>
> I am a beginner, only submit this patch for solved the problem of vector operand,  but don't think so far. I'm sorry that I can't answer this question. Could the designer @HsiangKai  help me to answer this question？

Initially, I model LMUL information into the instruction definitions. I created different operand classes for different LMUL register classes. After discussing with @rogfer01, we agreed to model the LMUL information into pseudo instructions. We will use the pseudo instructions to do code generation for RVV. There is no need to keep the operand class anymore.

I will create a patch to refine it. Thanks.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91668/new/

https://reviews.llvm.org/D91668