[PATCH] D91668: [RISCV]Add register constraint on riscv vector instruction

Tue Nov 17 18:36:49 PST 2020

tangxingxin1008 added a comment.

In D91668#2401307 <https://reviews.llvm.org/D91668#2401307>, @craig.topper wrote:

> In D91668#2401279 <https://reviews.llvm.org/D91668#2401279>, @jrtc27 wrote:
>
>> I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both `(reg)` and `0(reg)`, but that's irrelevant for vectors.
>
> I was wondering the same thing.

I am a beginner, only submit this patch for solved the problem of vector operand,  but don't think so far. I'm sorry that I can't answer this question. Could the designer @HsiangKai  help me to answer this question？

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  https://reviews.llvm.org/D91668/new/

https://reviews.llvm.org/D91668