[PATCH] D91668: [RISCV]Add register constraint on riscv vector instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D91668#2401279 <https://reviews.llvm.org/D91668#2401279>, @jrtc27 wrote:

> I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both `(reg)` and `0(reg)`, but that's irrelevant for vectors.

I was wondering the same thing.


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  https://reviews.llvm.org/D91668/new/

https://reviews.llvm.org/D91668