[PATCH] D91668: [RISCV]Add register constraint on riscv vector instruction

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both `(reg)` and `0(reg)`, but that's irrelevant for vectors.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D91668/new/

https://reviews.llvm.org/D91668