[PATCH] D91668: [RISCV]Add register constraint on riscv vector instruction

[eric tang via Phabricator via llvm-commits]

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  On vector instruction, if the operand is a vector, it should be from
  vector register groups.

Signed-off-by: tangxingxin <tangxingxin1008 at gmail.com>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91668

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/invalid.s


Index: llvm/test/MC/RISCV/rvv/invalid.s
===================================================================
--- llvm/test/MC/RISCV/rvv/invalid.s
+++ llvm/test/MC/RISCV/rvv/invalid.s
@@ -37,6 +37,9 @@
 vadd.vv v1, v3, v2, v0
 # CHECK-ERROR: expected '.t' suffix
 
+vadd.vv v1, v3, a0
+# CHECK-ERROR: invalid operand for instruction
+
 vmslt.vi v1, v2, -16
 # CHECK-ERROR: immediate must be in the range [-15, 16]
 
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -34,7 +34,7 @@
 def VRegAsmOperand : AsmOperandClass {
   let Name = "RVVRegOpOperand";
   let RenderMethod = "addRegOperands";
-  let PredicateMethod = "isReg";
+  let PredicateMethod = "isVR";
   let ParserMethod = "parseRegister";
 }
 
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -357,6 +357,11 @@
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
+  bool isVR() const {
+    return Kind == KindTy::Register &&
+           RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum);
+  }
+
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
                                   RISCVMCExpr::VariantKind &VK) {
     if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {


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