[PATCH] D90404: [AMDGPU] Add alignment check for v3 to v4 load type promotion

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D90404#2364971 <https://reviews.llvm.org/D90404#2364971>, @arsenm wrote:

> I'm not sure how I follow that 8 byte alignment is sufficient

If a dwordx3 load is 8-byte aligned then the three words loaded will be at addresses that are:
first word: 8 byte aligned
second word: 8 byte aligned + 4
third word: 8 byte aligned

Adding a fourth word to this load will put it at an address that is 8 byte aligned + 4, which is guaranteed to be in the same page as the third word, assuming your page size is greater than 4 bytes. So it can't cause any new page faults.


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https://reviews.llvm.org/D90404