[PATCH] D90162: [llvm][AArch64] Prevent spurious zero extention.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli marked an inline comment as done.
fpetrogalli added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1171
 
+bool SelectionDAG::isZeroExtendInReg(SDValue Val) const {
+  // assert(NarrowVT.isInteger() && "Unexpected EVT in input.");
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samparker wrote:
> There's so much existing logic around extensions and load widths that I'm struggling to believe that this is really needed... Maybe DAGCombiner::isAndLoadExtLoad can help instead?
Thank you for pointing this out!


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  https://reviews.llvm.org/D90162/new/

https://reviews.llvm.org/D90162