[PATCH] D90162: [llvm][AArch64] Prevent spurious zero extention.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli updated this revision to Diff 301218.
fpetrogalli added a comment.

I have removed the method `SelectionDAG::isZeroExtendInReg` in favour of using the machinery already available in `DAGCombiner`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90162/new/

https://reviews.llvm.org/D90162

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/zext-and-signed-compare.ll
  llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll

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