[PATCH] D90162: [llvm][AArch64] Prevent spurious zero extention.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:11300
+
+    return this->isAndLoadExtLoad(AndC, LoadN, LoadResultTy, ExtVT);
+  };
----------------
No need for this-> now.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:11314
+    // We care about the two different sign extension only if they are
+    // extending to the same EVT.
+    if (UseOne->getValueType(0) != UseTwo->getValueType(0))
----------------
Why are we only caring about those cases, couldn't this generally help mixed types too?


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:11318
+
+    if (UseOne->getOpcode() == ISD::SIGN_EXTEND_INREG && IsZeroExtInReg(UseTwo))
+      return true;
----------------
We already know that at least one use is SIGN_EXTEND_INREG node, so we shouldn't need to check again. Also, are UseOne and UseTwo guaranteed to be ordered the way you're expecting here? Maybe just iterate through all the uses looking for IsZeroExtInReg?


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  https://reviews.llvm.org/D90162/new/

https://reviews.llvm.org/D90162