[PATCH] D90162: [llvm][AArch64] Prevent spurious zero extention.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1171
 
+bool SelectionDAG::isZeroExtendInReg(SDValue Val) const {
+  // assert(NarrowVT.isInteger() && "Unexpected EVT in input.");
----------------
There's so much existing logic around extensions and load widths that I'm struggling to believe that this is really needed... Maybe DAGCombiner::isAndLoadExtLoad can help instead?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90162/new/

https://reviews.llvm.org/D90162