[PATCH] D90176: [AArch64] Improve lowering of insert_vector_elt with 0.0 consts.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

We could turn this into a more general combine,  We use fmov from a GPR to materialize fp constants in other cases.  But maybe just zero is fine to start.

> I am not sure if we can easily express this in the tablegen descriptions, because INS*vi*gpr is only defined for integer vectors and I am not sure how to convert things there.

MachineInstrs don't distinguish between integer and float vectors; there's only V64/V128 register classes.  So the types only matter for the inputs to tablegen patterns, not the outputs.  You can write a pattern that takes a float vector as an input and produces an INSvi32gpr without any casting.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9257
+  auto *CV = dyn_cast<ConstantFPSDNode>(Op.getOperand(1));
+  if (CV && CV->isZero()) {
+    using RowTy = MVT[3];
----------------
I think isZero is true for -0.0?


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  https://reviews.llvm.org/D90176/new/

https://reviews.llvm.org/D90176