[PATCH] D90176: [AArch64] Improve lowering of insert_vector_elt with 0.0 consts.

[Florian Hahn via Phabricator via llvm-commits]

fhahn updated this revision to Diff 301087.
fhahn added a comment.

Updated to make sure we do not do this transform for -0.0, thanks!

In D90176#2357309 <https://reviews.llvm.org/D90176#2357309>, @efriedma wrote:

> We could turn this into a more general combine,  We use fmov from a GPR to materialize fp constants in other cases.  But maybe just zero is fine to start.

So for other FP constants that have values that can be cheaply matrialized into GPRs? That would be good. I guess that would be helpful in all contexts where we can use GPRs directly instead of FPRs. Is there a way to match something like that generically?

Happy to look into that, but would prefer to start just with the 0.0 case.

>> I am not sure if we can easily express this in the tablegen descriptions, because INS*vi*gpr is only defined for integer vectors and I am not sure how to convert things there.
>
> MachineInstrs don't distinguish between integer and float vectors; there's only V64/V128 register classes.  So the types only matter for the inputs to tablegen patterns, not the outputs.  You can write a pattern that takes a float vector as an input and produces an INSvi32gpr without any casting.

Thanks! I think I was running into some ambiguity with the patterns, not sure exactly what was going on. Would you prefer the tablegen version?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90176/new/

https://reviews.llvm.org/D90176

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

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