[PATCH] D90176: [AArch64] Improve lowering of insert_vector_elt with 0.0 consts.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: efriedma, paquette, dmgreen, SjoerdMeijer.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
fhahn requested review of this revision.

When moving 0.0 into a float vector, we can use to vi*gpr variants of
INS. I am not sure if we can easily express this in the tablegen
descriptions, because INS*vi*gpr is only defined for integer vectors and
I am not sure how to convert things there.

This patch extends LowerINSERT_VECTOR_ELT to bitcast the input float
vector to an integer vector, apply the insertion and bitcast the result
back.

This way, we can piggy-back on the matching for the integer variants.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90176

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll

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