[PATCH] D90162: [llvm][AArch64] Prevent spurious zero extention.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli created this revision.
fpetrogalli added reviewers: peterwaller-arm, paulwalker-arm, efriedma.
Herald added subscribers: llvm-commits, ecnelises, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
fpetrogalli requested review of this revision.

This patch prevents generating a spurious zero extension of a sign
extended load, when the only use of the signed value is a comparison
that tests the sign bit of the signed extended value.

Now the compiler generates a zero extended load directly, and compares
the sign bit of the original unextended load instead of the sign
extended one.

The output code of (some of) the tests before and after the patch
looks as follows.

  BEFORE:                          |  AFTER:
  f_i32_i8:                        |  f_i32_i8:
          ldrsb   w9, [x0]         |      ldrb    w8, [x0]
          and     w8, w9, #0xff    |      tbnz    w8, #7, .LBB0_2
          tbnz    w9, #31, .LBB0_2 |      add     w0, w8, w8
          add     w0, w8, w8       |      ret
          ret                      |  .LBB0_2:
  .LBB0_2:                         |      mul     w0, w8, w8
          mul     w0, w8, w8       |      reT
          ret                      |
                                   |
  g_i32_i16:                       |  g_i32_i16:
          ldrsh   w8, [x0]         |      ldrh    w0, [x0]
          and     w0, w8, #0xffff  |      tbnz    w0, #15, .LBB3_2
          tbnz    w8, #31, .LBB3_2 |      ret
          ret                      |  .LBB3_2:
  .LBB3_2:                         |      lsl     w0, w0, #1
          lsl     w0, w0, #1       |      ret
          ret                      |


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D90162

Files:
  llvm/include/llvm/CodeGen/SelectionDAG.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/zext-and-signed-compare.ll
  llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll

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