[llvm] 2030db3 - [X86] Use mtriple instead of march in MIR tests

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-10-26T15:31:33Z
New Revision: 2030db328ae319b53c358923009f3d48d6fd4b52

URL: https://github.com/llvm/llvm-project/commit/2030db328ae319b53c358923009f3d48d6fd4b52
DIFF: https://github.com/llvm/llvm-project/commit/2030db328ae319b53c358923009f3d48d6fd4b52.diff

LOG: [X86] Use mtriple instead of march in MIR tests

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/opt_phis.mir
    llvm/test/CodeGen/X86/opt_phis2.mir
    llvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
    llvm/test/CodeGen/X86/x87-reg-usage.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/opt_phis.mir b/llvm/test/CodeGen/X86/opt_phis.mir
index f00ee76385dc..d9c63e3ebebf 100644
--- a/llvm/test/CodeGen/X86/opt_phis.mir
+++ b/llvm/test/CodeGen/X86/opt_phis.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass opt-phis -march=x86-64 -o - %s | FileCheck %s
+# RUN: llc -run-pass opt-phis -mtriple=x86_64-- -o - %s | FileCheck %s
 --- |
   define void @test() {
     ret void

diff  --git a/llvm/test/CodeGen/X86/opt_phis2.mir b/llvm/test/CodeGen/X86/opt_phis2.mir
index 3683d31db17b..7aca73411827 100644
--- a/llvm/test/CodeGen/X86/opt_phis2.mir
+++ b/llvm/test/CodeGen/X86/opt_phis2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass opt-phis -march=x86-64 -o - %s | FileCheck %s
+# RUN: llc -run-pass opt-phis -mtriple=x86_64-- -o - %s | FileCheck %s
 # All PHIs should be removed since they can be securely replaced
 # by %8 register.
 # CHECK-NOT: PHI

diff  --git a/llvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir b/llvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
index 08394756358b..1bdbc5386266 100644
--- a/llvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
+++ b/llvm/test/CodeGen/X86/unreachable-mbb-undef-phi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=x86-64 %s -o - -run-pass=processimpdefs -run-pass=unreachable-mbb-elimination | FileCheck %s
+# RUN: llc -mtriple=x86_64-- %s -o - -run-pass=processimpdefs -run-pass=unreachable-mbb-elimination | FileCheck %s
 ---
 name:            f
 tracksRegLiveness: true

diff  --git a/llvm/test/CodeGen/X86/x87-reg-usage.mir b/llvm/test/CodeGen/X86/x87-reg-usage.mir
index 8f9512cf7e82..6f4ff700db78 100644
--- a/llvm/test/CodeGen/X86/x87-reg-usage.mir
+++ b/llvm/test/CodeGen/X86/x87-reg-usage.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=x86-64 -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
+# RUN: llc -mtriple=x86_64-- -mattr=+x87 -mattr=-sse -run-pass none -o - %s | FileCheck %s
 # This test ensures that the MIR parser parses the x87 fpsw and fpcw regs
 
 --- |