[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoPseudoV.td:209
+// Pseudos.
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Defs = [VL, VTYPE] in {
+def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), []>;
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The PseudoVSETVLI  has the hasSideEffects = 1, mayLoad = 0, mayStore = 0


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https://reviews.llvm.org/D89449