[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1563
+
+  // For simplicity we reuse the vtype representation here.
+  // Bits | Name       | Description
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Perhaps this logic should go into RISCVBaseInfo, as I would expect other parts of the compiler will need to manipulate this operand's data at some point. It would be nice to have getters/setters for that, rather than relying on the underlying "encoding".


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Comment at: llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir:16
+  {
+    ret void
+  }
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Is this test function missing a body? I can't see how it would generate the expected MIR


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  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449