[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:208
+    llvm_unreachable("Unexpected pseudo instruction");
+  }
+  assert(MCInstr->getNumOperands() == 3 && "Unexpected instruction format");
----------------
May be
```
assert(MI.getOpcode() == RISCV::PseudoVSETVLI && "Unexpected pseudo instruction");
MCInstr = &TII.get(RISCV::VSETVLI);
```
is better


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1592
+    // SEWIndex must be >= 0
+    assert(SEWIndex >= 0);
+
----------------
may be 

```
assert(SEWIndex >= 0 && "SEWIndex must be >= 0");
```
is better


================
Comment at: llvm/utils/TableGen/GlobalISelEmitter.cpp:190
 
-  if (VT.isVector() && VT.getVectorNumElements() != 1)
+  if (VT.isScalableVector())
+    return None;
----------------
Is this if statement necessary?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449