[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

Committed. It looks like the legalisations seem reasonable. Something like:

  ; VBITS_EQ_256-DAG: and [[AND:z[0-9]+]].d, [[LO]].d, [[HI]].d
  ; VBITS_EQ_256-DAG: andv h[[REDUCE:[0-9]+]], [[PG]], [[AND]].h

How are the legalisation tests usually handled? Are they done once for a class of instructions? Or should I go back to add CHECKs for the other reductions too? @kmclaughlin


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https://reviews.llvm.org/D88707