[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D88707#2312081 <https://reviews.llvm.org/D88707#2312081>, @cameron.mcinally wrote:

> Committed. It looks like the legalisations seem reasonable. Something like:
>
>   ; VBITS_EQ_256-DAG: and [[AND:z[0-9]+]].d, [[LO]].d, [[HI]].d
>   ; VBITS_EQ_256-DAG: andv h[[REDUCE:[0-9]+]], [[PG]], [[AND]].h
>
> How are the legalisation tests usually handled? Are they done once for a class of instructions? Or should I go back to add CHECKs for the other reductions too? @kmclaughlin

In general I've tried to always add VBITS_EQ_256 check lines to any test that also has VBITS_GE_512 check lines.


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https://reviews.llvm.org/D88707