[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation

[Cameron McInally via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9642ded8ba64: [SVE] Lower fixed length VECREDUCE_AND operation (authored by cameron.mcinally).

Changed prior to commit:
  https://reviews.llvm.org/D88707?vs=295679&id=296202#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88707/new/

https://reviews.llvm.org/D88707

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D88707.296202.patch
Type: text/x-patch
Size: 18719 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201005/c5ef1411/attachment-0001.bin>