[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation
Cameron McInally via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 5 09:34:42 PDT 2020
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9642ded8ba64: [SVE] Lower fixed length VECREDUCE_AND operation (authored by cameron.mcinally).
Changed prior to commit:
https://reviews.llvm.org/D88707?vs=295679&id=296202#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D88707/new/
https://reviews.llvm.org/D88707
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
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