[PATCH] D88707: [SVE] Lower fixed length VECREDUCE_AND operation

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll:67
+; VBITS_GE_512-NEXT: fmov w0, s[[REDUCE]]
+; VBITS_GE_512-NEXT: ret
+  %op = load <64 x i8>, <64 x i8>* %a
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Can you add VBITS_EQ_256 check lines to the VBITS_GE_512 related tests to ensure sensible type legalisation. See sve-fixed-length-int-minmax.ll for example.  It looks like I missed this for the other reduction tests.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D88707/new/

https://reviews.llvm.org/D88707