[PATCH] D87384: [PowerPC] Add ISEL patterns for Mul with Imm.

[EsmeYi via Phabricator via llvm-commits]

Esme added a comment.

Hi @jsji  Infinite loop will occur if we handle the scenario 1 ` (mul X, c2 << c1) ->  (mul (shl X, c1), c2)` in DAGCombiner, because there exists a reverse conversion `(mul (shl X, c1), c2) -> (mul X, c2 << c1)`.


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  https://reviews.llvm.org/D87384/new/

https://reviews.llvm.org/D87384